Please use this identifier to cite or link to this item: https://doi.org/10.1109/IWJT.2010.5474988
Title: Advanced source/drain technologies for parasitic resistance reduction
Authors: Yeo, Y.-C. 
Issue Date: 2010
Source: Yeo, Y.-C. (2010). Advanced source/drain technologies for parasitic resistance reduction. IWJT-2010: Extended Abstracts - 2010 International Workshop on Junction Technology : 57-61. ScholarBank@NUS Repository. https://doi.org/10.1109/IWJT.2010.5474988
Abstract: To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide contact and the source/drain region in n- and p-FETs will be examined. Integration of these approaches in advanced device architectures will be shown. © 2010 IEEE.
Source Title: IWJT-2010: Extended Abstracts - 2010 International Workshop on Junction Technology
URI: http://scholarbank.nus.edu.sg/handle/10635/69244
ISBN: 9781424458691
DOI: 10.1109/IWJT.2010.5474988
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