A space vector PWM scheme to reduce common mode voltage for a cascaded multilevel inverter

Abstract

Multilevel inverters generate common mode voltage similar to two-level inverters. Schemes have been reported for multilevel inverters to reduce the common mode voltage. However, most of the schemes result in reduced modulation depth, high switching losses and high harmonic distortion. This paper proposes a simple space vector PWM scheme to reduce common mode voltage for cascaded multilevel inverter and addresses these issues. The scheme is explained for S-level inverter. The scheme can be easily extended to a n-level inverter. Both experimental and simulation results are provided.