Please use this identifier to cite or link to this item: https://doi.org/10.1109/EDSSC.2005.1635218
Title: A simulation study of FIBL in Ge MOSFETs with high-k gate dielectrics
Authors: Tan, Y.P.
James, M.-K.L.
Zhang, Q.
Wu, N.
Zhu, C. 
Issue Date: 2006
Source: Tan, Y.P.,James, M.-K.L.,Zhang, Q.,Wu, N.,Zhu, C. (2006). A simulation study of FIBL in Ge MOSFETs with high-k gate dielectrics. 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC : 111-113. ScholarBank@NUS Repository. https://doi.org/10.1109/EDSSC.2005.1635218
Abstract: The effect of fringe induced barrier lowering (FIBL) in Ge MOSFETs with high-k gate dielectrics is simulated with comparison to those of Si counterparts. It is observed that both Ge and Si devices undergo FIBL, which is dependent on gate length and permittivity of gate dielectrics. Germanium MOSFETs show less vulnerable FIBL effects than silicon counterparts in terms of DIBL and sub-threshold swing due to a higher permittivity in Ge. It is concluded that although FIBL cannot be eliminated, it will not be an issue if the gate relative permittivity used is small. © 2005 IEEE.
Source Title: 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
URI: http://scholarbank.nus.edu.sg/handle/10635/69075
ISBN: 0780393392
DOI: 10.1109/EDSSC.2005.1635218
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