Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2009.5118069
Title: A quasi-delay-insensitive dual-rail adder working in subthreshold region
Authors: Xiaofei, C.
Yong, L. 
Issue Date: 2009
Source: Xiaofei, C.,Yong, L. (2009). A quasi-delay-insensitive dual-rail adder working in subthreshold region. Proceedings - IEEE International Symposium on Circuits and Systems : 1569-1572. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2009.5118069
Abstract: In this paper, we propose a novel design of quasi-delay-insensitive dual-rail asynchronous adder working at subthreshold region using 0.13μm standard CMOS technologies. Power Delay Product (PDP) as measure of merit is used for comparison with other recent published subthreshold adders. Low-power consumption, low PDP and high robustness are demonstrated. ©2009 IEEE.
Source Title: Proceedings - IEEE International Symposium on Circuits and Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/69028
ISBN: 9781424438280
ISSN: 02714310
DOI: 10.1109/ISCAS.2009.5118069
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