Please use this identifier to cite or link to this item: https://doi.org/10.1109/CIT.2005.3
Title: A compiler-controlled instruction cache architecture for an embedded low power microprocessor
Authors: Zhu, X.
Tay, T.T. 
Issue Date: 2005
Citation: Zhu, X., Tay, T.T. (2005). A compiler-controlled instruction cache architecture for an embedded low power microprocessor. Proceedings - Fifth International Conference on Computer and Information Technology, CIT 2005 2005 : 815-821. ScholarBank@NUS Repository. https://doi.org/10.1109/CIT.2005.3
Abstract: Modern microprocessors have been improving their performance with deeper sub-micron technologies and larger on-chip cache memories. This trend leads to a dramatic increment of power consumption in such units and has prompted researchers to develop power efficient caches. Here we propose a method that dynamically turns off those unused cache lines to save power at architecture level. In our algorithm, the object codes of programs are reallocated in memory address map so that the working sets are reduced when they are loaded into I-cache. In addition, a few special cache-scaling instructions (CSIs) are added to the object codes to track the working set sizes. With the information from CSIs and the current system state, a hardware controller implements the decision of caching instructions and scales the size of cache memory. Experimental results using popular Windows-based applications show that the compiler-controlled resizable cache can reduce 55.8% of energy in a 32K I-cache with only 2.9% of performance degradation on average. © 2005 IEEE.
Source Title: Proceedings - Fifth International Conference on Computer and Information Technology, CIT 2005
URI: http://scholarbank.nus.edu.sg/handle/10635/68749
DOI: 10.1109/CIT.2005.3
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