Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASSCC.2010.5716613
Title: A 60 GHz heterodyne quadrature transmitter with a new simplified architecture in 90nm CMOS
Authors: Brinkhoff, J.
Lin, F.
Kang, K.
Pham, D.-D.
Heng, C.-H. 
Issue Date: 2010
Source: Brinkhoff, J.,Lin, F.,Kang, K.,Pham, D.-D.,Heng, C.-H. (2010). A 60 GHz heterodyne quadrature transmitter with a new simplified architecture in 90nm CMOS. 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 : 293-296. ScholarBank@NUS Repository. https://doi.org/10.1109/ASSCC.2010.5716613
Abstract: A 60 GHz heterodyne up-convertor consuming only 29 mW, together with a PA consuming 84 mW, is presented. It is implemented in 90nm CMOS. It takes advantage of sub-harmonic mixing and a sliding IF architecture, using a single LO around the relatively low frequency of 20 GHz, thus relaxing millimeter-wave LO design. This also allowed LO buffers to be eliminated, which minimizes area and power consumption. The I/Q up-converter includes a quadrature VCO, resistive IF mixers, IF amplifier and RF sub-harmonic mixer. It achieves a tuning range of 8.8 % and a conversion gain of 13.1 dB. The 60 GHz power amplifier delivers 9.8 dBm, has 9.7 % PAE and 20 dB gain. ©2010 IEEE.
Source Title: 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
URI: http://scholarbank.nus.edu.sg/handle/10635/68713
ISBN: 9781424482979
DOI: 10.1109/ASSCC.2010.5716613
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