A 1 GHz decimation filter for Sigma-Delta ADC

Please use this identifier to cite or link to this item: https://doi.org/10.1109/MWSCAS.2007.4488614

Title:	A 1 GHz decimation filter for Sigma-Delta ADC
Authors:	Lian, Y. Wei, Y. Chandrasekaran, R.
Issue Date:	2007
Citation:	Lian, Y.,Wei, Y.,Chandrasekaran, R. (2007). A 1 GHz decimation filter for Sigma-Delta ADC. Midwest Symposium on Circuits and Systems : 401-404. ScholarBank@NUS Repository. https://doi.org/10.1109/MWSCAS.2007.4488614
Abstract:	This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-flop. The filter has been implemented in a 0.18μm/ 1.8 V CMOS technology for a decimation factor of 4. The operation frequency is 1 GHz and the power consumption of I and Q filters are 6 mW and 4 mW, respectively. © 2007 IEEE.
Source Title:	Midwest Symposium on Circuits and Systems
URI:	http://scholarbank.nus.edu.sg/handle/10635/68696
ISBN:	1424411769
ISSN:	15483746
DOI:	10.1109/MWSCAS.2007.4488614
Appears in Collections:	Staff Publications

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