Please use this identifier to cite or link to this item:
|Title:||A 0.18-μm CMOS UWB LNA with 5 GHz interference rejection|
Low-noise amplifier (LNA)
|Citation:||Gao, Y., Zheng, Y., Ooi, B.-L. (2007). A 0.18-μm CMOS UWB LNA with 5 GHz interference rejection. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium : 47-50. ScholarBank@NUS Repository. https://doi.org/10.1109/RFIC.2007.380830|
|Abstract:||A ultra-wideband low noise amplifier (LNA) with integrated notch filter for interference rejection is designed using 0.18-μm CMOS technology. The three-stage LNA employs a current reuse structure to reduce the power consumption and a serial LC circuit with Q-enhancement circuit to produce band rejection in the 5-6GHz frequency band. The load tank optimization for the current reuse stage is discussed for gain flatness tuning. Measurements show that this LNA has a peak gain of 21.5dB in the low band (3-5GHz) and 15dB in the high band (6-10GHz) while consuming 12mA of current from a 1.8V DC supply. The measured noise figure (NF) and IIP3 are 4.0dB and -18.5 dBm at 3.5GHz, 5.1 dB and -15.5 dBm at 7.2GHz respectively. A 6-12dB gain notch in the 5-6GHz is realized for interference rejection. © 2007 IEEE.|
|Source Title:||Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Nov 12, 2018
WEB OF SCIENCETM
checked on Oct 17, 2018
checked on Nov 9, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.