Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2002.805750
Title: Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling
Authors: Chen, G. 
Li, M.F. 
Ang, C.H.
Zheng, J.Z.
Kwong, D.L.
Keywords: Annealing
CMOSFETs
Negative bias temperature instability (NBTI)
Semiconductor-insulator interfaces
Ultrathin gate oxide
Issue Date: Dec-2002
Citation: Chen, G., Li, M.F., Ang, C.H., Zheng, J.Z., Kwong, D.L. (2002-12). Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling. IEEE Electron Device Letters 23 (12) : 734-736. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2002.805750
Abstract: For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/67902
ISSN: 07413106
DOI: 10.1109/LED.2002.805750
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