Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/62931
Title: VLSI design for implementation of transform domain adaptive filters
Authors: Najafi, A.
Farhang-Boroujeny, B. 
Samudra, G.S. 
Issue Date: 1999
Source: Najafi, A.,Farhang-Boroujeny, B.,Samudra, G.S. (1999). VLSI design for implementation of transform domain adaptive filters. VLSI Design 9 (2) : 119-133. ScholarBank@NUS Repository.
Abstract: A VLSI implementation of a dedicated digital signal processor is presented. The processor is tailored for efficient implementation of transform domain adaptive filters. It incorporates a butterfly processor which performs butterfly operation to implement the required transformation. It is also able to perform complex addition, subtraction and multiplication. The butterfly processor makes use of a redundant binary tree multiplier with a recently proposed coding of signed-digit numbers which reduces the number of levels in the tree by one. An on-chip read only memory holds the transformation coefficients. The contents of the ROM determine the type of transform. The processor incorporates an ALU to perform integer arithmetic, address calculations and implementation of circular memory scheme. For fastest accessibility, the essential variables of the algorithm are implemented in a register fire.
Source Title: VLSI Design
URI: http://scholarbank.nus.edu.sg/handle/10635/62931
ISSN: 1065514X
Appears in Collections:Staff Publications

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