Please use this identifier to cite or link to this item:
|Title:||An efficient bit-serial FIR filter architecture|
|Authors:||Lim, Y.C. |
|Citation:||Lim, Y.C., Evans, J.B., Liu, B. (1995-09). An efficient bit-serial FIR filter architecture. Circuits, Systems, and Signal Processing 14 (5) : 639-651. ScholarBank@NUS Repository. https://doi.org/10.1007/BF01213960|
|Abstract:||A new bit-serial architecture for implementation of high order FIR filters is introduced, as well as example FPGA and CMOS realizations. This structure exploits the simplicity of coefficients that consist of two power-of-two terms to yield efficient implementations. Quantization effects are discussed and a simple block scaling method for reducing rounding and truncation noise in high order filters is also presented. © 1995 Birkhäuser.|
|Source Title:||Circuits, Systems, and Signal Processing|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on May 22, 2018
WEB OF SCIENCETM
checked on May 15, 2018
checked on Feb 25, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.