Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.mee.2004.04.001
Title: Performance improvement in gate level lithography using resolution enhancement techniques
Authors: Chua, G.S.
Tay, C.J. 
Quan, C. 
Lin, Q.
Keywords: Assist features
Depth of focus
Optical proximity correction
Resolution enhancement technique
Scattering bars
Issue Date: Aug-2004
Source: Chua, G.S., Tay, C.J., Quan, C., Lin, Q. (2004-08). Performance improvement in gate level lithography using resolution enhancement techniques. Microelectronic Engineering 75 (2) : 155-164. ScholarBank@NUS Repository. https://doi.org/10.1016/j.mee.2004.04.001
Abstract: Downscaling of critical dimensions in semiconductor circuits has been pushing photolithography to print features below the wavelength of the light source. However, severe optical proximity effects and small depth of focus (DOF) for isolated lines have brought challenges to sub-wavelength lithography for application to 0.10 μm technology using 248 and 193 nm scanners. In this paper, the use of attenuated PSM (attPSM), annular illumination and SB-OPC techniques are investigated and elaborated on the gate level lithography for the 0.10 μm technology node. The study focus on lithographic improvement applying scattering bar (SB)-OPC, reducing λ from 248 to 193 nm, using attPSM over binary mask and comparing conventional with annular illumination for the 100 nm technology node. Simulations are used to determine the optimal SB width and placement position for 100 nm lines through pitch. Experimental results are used to support the discussions in the manuscript. It is showed that SB with OPC for attPSM is effective for enlarging the common DOF of isolated and dense pattern and therefore critical for achieving acceptable 0.10 μm CD process. © 2004 Elsevier B.V. All rights reserved.
Source Title: Microelectronic Engineering
URI: http://scholarbank.nus.edu.sg/handle/10635/61070
ISSN: 01679317
DOI: 10.1016/j.mee.2004.04.001
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