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Title: Optimization of the thermomechanical reliability of a 65 nm Cu/Low-k large-die flip chip package
Authors: Ong, J.M.G.
Tay, A.A.O. 
Zhang, X.
Kripesh, V.
Lim, Y.K.
Yeo, D.
Chan, K.C.
Tan, J.B.
Hsia, L.C.
Sohn, D.K.
Keywords: 65 nm Cu/low-k
Finite element analysis
Flip chip package
Solder joint reliability
Issue Date: Dec-2009
Citation: Ong, J.M.G., Tay, A.A.O., Zhang, X., Kripesh, V., Lim, Y.K., Yeo, D., Chan, K.C., Tan, J.B., Hsia, L.C., Sohn, D.K. (2009-12). Optimization of the thermomechanical reliability of a 65 nm Cu/Low-k large-die flip chip package. IEEE Transactions on Components and Packaging Technologies 32 (4) : 838-848. ScholarBank@NUS Repository.
Abstract: The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm ×21 mm die size flip-chip ball grid array package incorporated with fully active and functional nine-metal Cu/low-k layers and 150 μ m interconnect pitch. The low-k material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built large-die package, reliability tests were carried out on some existing 15 mm ×,15 mm die Cu/low-k flip chip packages which were identical to the 21 mm ×,21 mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm ×,15 mm die. The computed delamination stresses at the low- k layer and the strain energy density dissipation per cycle in the critical solder (Δ W) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and Δ W were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and Δ W are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages. © 2009 IEEE.
Source Title: IEEE Transactions on Components and Packaging Technologies
ISSN: 15213331
DOI: 10.1109/TCAPT.2009.2020696
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