Please use this identifier to cite or link to this item: https://doi.org/10.1016/j.microrel.2008.12.013
Title: Mapping the failure envelope of board-level solder joints
Authors: Tan, L.B.
Zhang, X.
Lim, C.T. 
Tan, V.B.C. 
Issue Date: Apr-2009
Source: Tan, L.B.,Zhang, X.,Lim, C.T.,Tan, V.B.C. (2009-04). Mapping the failure envelope of board-level solder joints. Microelectronics Reliability 49 (4) : 397-409. ScholarBank@NUS Repository. https://doi.org/10.1016/j.microrel.2008.12.013
Abstract: Single solder interconnects were subjected to a series of combined tension-shear and compression-shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability. © 2009.
Source Title: Microelectronics Reliability
URI: http://scholarbank.nus.edu.sg/handle/10635/60674
ISSN: 00262714
DOI: 10.1016/j.microrel.2008.12.013
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