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|Title:||Analytical solutions for interconnect stress in board level drop impact|
Integrated circuit manufacture
|Citation:||Wong, E.H., Mai, Y.-W., Seah, S.K.W., Lim, K.-M., Lim, T.B. (2007-11). Analytical solutions for interconnect stress in board level drop impact. IEEE Transactions on Advanced Packaging 30 (4) : 654-664. ScholarBank@NUS Repository. https://doi.org/10.1109/TADVP.2007.898599|
|Abstract:||Closed form analytical solutions for the stresses in the interconnects between the integrated circuit (IC) package and the printed circuit board (PCB) when the PCB assembly is subjected to a mechanical shock have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnects when subjected to mechanical shock, and have been used to establish the following key findings: 1) for the same magnitude of strain measured on the PCB, symmetric bending will result in the highest stress in the interconnect while anti-symmetric bending will result in the least stress; 2) the cross-section area of the interconnect is the single most critical parameter; 3) the eight-layer buildup board specified in JEDEC standard JESD22-B111 can be replaced with an equivalent conventional board that exhibits similar natural frequency as the eight-layer buildup board. © 2007 IEEE.|
|Source Title:||IEEE Transactions on Advanced Packaging|
|Appears in Collections:||Staff Publications|
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