Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2008.923712
Title: Source and drain series resistance reduction for N-channel transistors using solid antimony (Sb) segregation (SSbS) during silicidation
Authors: Wong, H.-S.
Koh, A.T.-Y.
Chin, H.-C.
Chan, L.
Samudra, G. 
Yeo, Y.-C. 
Keywords: Antimony segregation
Parasitic series resistance
Salicidation
Schottky barrier (SB)
Issue Date: Jul-2008
Source: Wong, H.-S., Koh, A.T.-Y., Chin, H.-C., Chan, L., Samudra, G., Yeo, Y.-C. (2008-07). Source and drain series resistance reduction for N-channel transistors using solid antimony (Sb) segregation (SSbS) during silicidation. IEEE Electron Device Letters 29 (7) : 756-758. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2008.923712
Abstract: We report the first integration of a novel solid Antimony (Sb) segregation (SSbS) process in a transistor fabrication flow. A thin solid Sb layer, which acts as a large source of n-type dopants, was deposited beneath a metallic nickel layer prior to source-drain silicidation. Following nickel silicidation, a very high concentration of Sb was incorporated at the NiSi/Si interface. The SSbS process is demonstrated to reduce the effective Schottky barrier (SB) height and parasitic series resistance in an n-channel field-effect transistor, leading to enhanced drive current performance without degradation in the OFF-state leakage current. Performance enhancement is also maintained when the supply voltage is reduced from 1.3 to 0.8 V. © 2008 IEEE.
Source Title: IEEE Electron Device Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/57448
ISSN: 07413106
DOI: 10.1109/LED.2008.923712
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