Please use this identifier to cite or link to this item: https://doi.org/10.1063/1.2430924
Title: Performance enhancement of n-channel impact-ionization metal-oxide- semiconductor transistor by strain engineering
Authors: Toh, E.-H.
Wang, G.H.
Lo, G.-Q.
Chan, L.
Samudra, G. 
Yeo, Y.-C. 
Issue Date: 2007
Source: Toh, E.-H., Wang, G.H., Lo, G.-Q., Chan, L., Samudra, G., Yeo, Y.-C. (2007). Performance enhancement of n-channel impact-ionization metal-oxide- semiconductor transistor by strain engineering. Applied Physics Letters 90 (2) : -. ScholarBank@NUS Repository. https://doi.org/10.1063/1.2430924
Abstract: The introduction of lattice strain in impact-ionization metal-oxide-semiconductor (I-MOS) transistors for performance enhancement is reported. Lattice strain affects impact ionization and its impact on device performance is explained in relation to the physics of I-MOS device operation. By integrating epitaxial silicon-carbon (Si0.99 C0.01) source and drain regions in a complementary-MOS-compatible fabrication process, strained n -channel I-MOS devices were fabricated. Tensile strain in the channel and impact-ionization regions contributes to enhanced electron transport and device characteristics. The strained I-MOS technology demonstrates an excellent subthreshold swing of 5.3 mVdecade at room temperature. Compared to control I-MOS devices with Si raised source/drain, strained I-MOS devices show significantly higher drive current and a steeper subthreshold swing. © 2007 American Institute of Physics.
Source Title: Applied Physics Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/57026
ISSN: 00036951
DOI: 10.1063/1.2430924
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