Please use this identifier to cite or link to this item:
|Title:||Metal gate technology for nanoscale transistors - Material selection and process integration issues|
|Keywords:||High-k dielectric materials|
|Source:||Yeo, Y.-C. (2004-09). Metal gate technology for nanoscale transistors - Material selection and process integration issues. Thin Solid Films 462-463 (SPEC. ISS.) : 34-41. ScholarBank@NUS Repository. https://doi.org/10.1016/j.tsf.2004.05.039|
|Abstract:||Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replacement of the conventional poly-Si gate material with metal gate materials. A metal gate material not only eliminates the gate depletion and dopant penetration problems but also greatly reduces the gate sheet resistance. In this paper, we discuss the material requirements for metal gate CMOS technology and the challenges involved in the integration of metal gate electrodes in a nanoscale transistor. Issues addressed include the choice of metal gate materials for conventional bulk and advanced transistor structures, the physics of the metal-dielectric interface, and the process integration of these materials in a CMOS process. © 2004 Published by Elsevier B.V.|
|Source Title:||Thin Solid Films|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Mar 7, 2018
WEB OF SCIENCETM
checked on Jan 29, 2018
checked on Mar 11, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.