Please use this identifier to cite or link to this item: https://doi.org/10.1109/TCAD.2010.2042887
Title: Iterative probabilistic performance prediction for multi-application multiprocessor systems
Authors: Kumar, A. 
Mesman, B.
Corporaal, H.
Ha, Y. 
Keywords: Heterogeneous multiprocessor
Multiple applications
Non-preemption
Performance prediction
Synchronous data flow graphs
Issue Date: Apr-2010
Source: Kumar, A., Mesman, B., Corporaal, H., Ha, Y. (2010-04). Iterative probabilistic performance prediction for multi-application multiprocessor systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29 (4) : 538-551. ScholarBank@NUS Repository. https://doi.org/10.1109/TCAD.2010.2042887
Abstract: Modern embedded devices are increasingly becoming multiprocessor with the need to support a large number of applications to satisfy the demands of users. Due to a huge number of possible combinations of these multiple applications, it becomes a challenge to predict their performance. This becomes even more important when applications may be dynamically started and stopped in the system. Since modern embedded systems allow users to download and add applications at run-time, a complete design-time analysis is not always possible. This paper presents a new technique to accurately predict the performance of multiple applications mapped on a multiprocessor platform. Iterative probabilistic analysis is used to estimate the time spent by tasks during their contention phase, and thereby predicting the performance of applications. The approach is scalable with the number of applications and processors in the system. As compared to earlier techniques, this approach is much faster and scalable, while still improving the accuracy. The analysis takes 300 μs on a 500 MHz processor for ten applications. Since multimedia applications are increasingly becoming more dynamic, results of a case-study with applications with varying execution times are also presented. In addition, results of a case-study with real applications executing on a field-programmable gate array multiprocessor platform are shown. © 2010 IEEE.
Source Title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/56430
ISSN: 02780070
DOI: 10.1109/TCAD.2010.2042887
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