Please use this identifier to cite or link to this item: https://doi.org/10.1116/1.2198849
Title: Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack
Authors: Joo, M.S. 
Park, C.S. 
Cho, B.J. 
Balasubramanian, N.
Kwong, D.-L.
Issue Date: May-2006
Source: Joo, M.S., Park, C.S., Cho, B.J., Balasubramanian, N., Kwong, D.-L. (2006-05). Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack. Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures 24 (3) : 1341-1343. ScholarBank@NUS Repository. https://doi.org/10.1116/1.2198849
Abstract: Metal-induced gap states (MIGS) theory is applied to fully silicided (FUSI) gate for the investigation of Fermi-level pinning at the interface of FUSI gate and high- K dielectrics. Using the combination of semiempirical approach and MIGS theory, it has been found that FUSI gate has effectively M Si2 configuration at the interface with gate dielectrics. The vacuum work function values of several FUSI gates have been obtained through the analysis, and it has also been found that the Fermi-level pinning behavior of FUSI gate on high- K dielectric follows the MIGS theory well. FUSI gate on high- K dielectric shows much weaker Fermi-level pinning compared with polysilicon gate on high K dielectric, which is another attractive advantage of FUSI gate process. © 2006 American Vacuum Society.
Source Title: Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
URI: http://scholarbank.nus.edu.sg/handle/10635/56367
ISSN: 10711023
DOI: 10.1116/1.2198849
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