Please use this identifier to cite or link to this item: https://doi.org/10.1142/S0218194005002014
Title: HW/SW co-design for low power arithmetic and logic units
Authors: Tiow, T.T. 
Sin, N.K.
Yan, P.
Keywords: Arithmetic Logic Unit design
Instruction interdependence
Instruction scheduling
Issue Date: Apr-2005
Source: Tiow, T.T.,Sin, N.K.,Yan, P. (2005-04). HW/SW co-design for low power arithmetic and logic units. International Journal of Software Engineering and Knowledge Engineering 15 (2) : 335-341. ScholarBank@NUS Repository. https://doi.org/10.1142/S0218194005002014
Abstract: 7As many embedded microprocessors are battery driven, low power design is becoming increasingly necessary. In this paper, we proposed hardware-software co-design architecture for low power arithmetic and logic units. By including multiple functional units with the same functions and different speeds, we provide instruction implementations at various power prices. Then, with an assembler level scheduler, we identify and create situations whereby the low-power slow functional units can be utilized. The overall performance is not compromised as no additional stalls are introduced. Simulations show 10%∼35% power saving in typical addition operations. © World Scientific Publishing Company.
Source Title: International Journal of Software Engineering and Knowledge Engineering
URI: http://scholarbank.nus.edu.sg/handle/10635/56225
ISSN: 02181940
DOI: 10.1142/S0218194005002014
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