Please use this identifier to cite or link to this item: https://doi.org/10.1063/1.2363144
Title: Effective suppression of Fermi level pinning in polycrystalline-silicon/ high- k gate stack by using polycrystalline-silicon-germanium gate electrode
Authors: Yu, X.
Zhu, C. 
Yu, M.
Issue Date: 2006
Source: Yu, X., Zhu, C., Yu, M. (2006). Effective suppression of Fermi level pinning in polycrystalline-silicon/ high- k gate stack by using polycrystalline-silicon-germanium gate electrode. Applied Physics Letters 89 (16) : -. ScholarBank@NUS Repository. https://doi.org/10.1063/1.2363144
Abstract: In this study, the crucial issue of unacceptably high threshold voltage (Vth) induced by Fermi level pinning in poly-Si/high- k complementary metal-oxide-semiconductor field-effect transistor (MOSFET) was effectively suppressed by inserting a poly-SiGe gate electrode. The Vth of -1.02 V in poly- SiHfO2 p -channel MOSFET was tuned to -0.81 V in poly- Si Al2 O3 Hf O2 and further reduced to -0.49 V in poly-Si/poly- SiGe Al2 O3 Hf O2 gate stack. Meanwhile, the Vth of 0.3 V was achieved in the n -channel MOSFET with the poly-SiGe gate. Moreover, transconductance and Vth stability in the MOSFETs with poly-SiGe gate were remarkably improved compared to poly- SiHf O2 and poly- Si Al2 O3 Hf O2 devices. The low Vth and good Vth stability observed in the devices with poly-SiGe gate may be mainly attributed to the suppressed formation of oxygen vacancies in high- k gate dielectric, which is commonly believed to cause the Fermi level pinning effect in poly-Si/high- k device. © 2006 American Institute of Physics.
Source Title: Applied Physics Letters
URI: http://scholarbank.nus.edu.sg/handle/10635/55767
ISSN: 00036951
DOI: 10.1063/1.2363144
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