Please use this identifier to cite or link to this item: https://doi.org/10.1143/JJAP.47.2593
Title: Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium source
Authors: Toh, E.-H.
Wang, G.H.
Chan, L.
Sylvester, D.
Heng, C.-H. 
Samudra, G.S. 
Yeo, Y.-C. 
Keywords: Double-gate
Silicon- germanium
Subthreshold swing
TFET
Tunneling
Issue Date: 25-Apr-2008
Source: Toh, E.-H., Wang, G.H., Chan, L., Sylvester, D., Heng, C.-H., Samudra, G.S., Yeo, Y.-C. (2008-04-25). Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium source. Japanese Journal of Applied Physics 47 (4 PART 2) : 2593-2597. ScholarBank@NUS Repository. https://doi.org/10.1143/JJAP.47.2593
Abstract: A novel double-gate (DG) tunneling field-effect transistor (TFET) with silicon - germanium (SiGe) Source is proposed to overcome the scaling limits of complementary metal - oxide - semiconductor (CMOS) technology and further extends Moore's law. The narrower bandgap of the SiGe source helps to reduce the tunneling width and improves the subthreshold swing and on-state current. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. For the first time, we show that such a technology proves to be viable to replace CMOS for high performance, low standby power, and low power technologies through the end of the roadmap with extensive simulations. © 2008 The Japan Society of Applied Physics.
Source Title: Japanese Journal of Applied Physics
URI: http://scholarbank.nus.edu.sg/handle/10635/55624
ISSN: 00214922
DOI: 10.1143/JJAP.47.2593
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