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Title: Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Authors: Singh, A.K.
Srikanthan, T.
Kumar, A. 
Jigang, W.
Keywords: Hardware-software co-design
Heterogeneous architectures
Mapping algorithms
MPSoC design
Network-on-Chip (NoC)
Issue Date: Jul-2010
Citation: Singh, A.K., Srikanthan, T., Kumar, A., Jigang, W. (2010-07). Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. Journal of Systems Architecture 56 (7) : 242-255. ScholarBank@NUS Repository.
Abstract: Efficient run-time mapping of tasks onto Multiprocessor System-on-Chip (MPSoC) is very challenging especially when new tasks of other applications are also required to be supported at run-time. In this paper, we present a number of communication-aware run-time mapping heuristics for the efficient mapping of multiple applications onto an MPSoC platform in which more than one task can be supported by each processing element (PE). The proposed mapping heuristics examine the available resources prior to recommending the adjacent communicating tasks on to the same PE. In addition, the proposed heuristics give priority to the tasks of an application in close proximity so as to further minimize the communication overhead. Our investigations show that the proposed heuristics are capable of alleviating Network-on-Chip (NoC) congestion bottlenecks when compared to existing alternatives. We map tasks of applications onto an 8 × 8 NoC-based MPSoC to show that our mapping heuristics consistently leads to reduction in the total execution time, energy consumption, average channel load and latency. In particular, we show that energy savings can be up to 44% and average channel load is improved by 10% for some cases. © 2010 Elsevier B.V. All rights reserved.
Source Title: Journal of Systems Architecture
ISSN: 13837621
DOI: 10.1016/j.sysarc.2010.04.007
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