Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2008.919308
Title: Analysis of the effects of fringing electric field on finFET device performance and structural optimization using 3-D simulation
Authors: Zhao, H.
Yeo, Y.-C. 
Rustagi, S.C.
Samudra, G.S.
Keywords: Capacitance
FinFET
Fringing electric field
Simulation
Issue Date: May-2008
Source: Zhao, H., Yeo, Y.-C., Rustagi, S.C., Samudra, G.S. (2008-05). Analysis of the effects of fringing electric field on finFET device performance and structural optimization using 3-D simulation. IEEE Transactions on Electron Devices 55 (5) : 1177-1184. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2008.919308
Abstract: In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher κ value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high-κ gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE. © 2008 IEEE.
Source Title: IEEE Transactions on Electron Devices
URI: http://scholarbank.nus.edu.sg/handle/10635/55096
ISSN: 00189383
DOI: 10.1109/TED.2008.919308
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