Please use this identifier to cite or link to this item: https://doi.org/10.1109/TADVP.2007.898617
Title: A novel test strategy for fine pitch wafer-level packaged devices
Authors: Jayabalan, J.
Rotaru, M.D.
Rao, V.S.
Kripesh, V.
Iyer, M.K.
Tay, A.A.O. 
Ooi, B.-L. 
Leong, M.-S. 
Keywords: Coplanar probe
ELastomer mesh substrate
Multigigahertz test
Wafer-level package test and characterization
Issue Date: Aug-2007
Source: Jayabalan, J., Rotaru, M.D., Rao, V.S., Kripesh, V., Iyer, M.K., Tay, A.A.O., Ooi, B.-L., Leong, M.-S. (2007-08). A novel test strategy for fine pitch wafer-level packaged devices. IEEE Transactions on Advanced Packaging 30 (3) : 439-447. ScholarBank@NUS Repository. https://doi.org/10.1109/TADVP.2007.898617
Abstract: This paper describes an innovative test strategy comprising a compliant elastomer mesh for testing fine pitch wafer-level package (WLP) devices. The test probe, hardware, and sample preparation processes are detailed. The components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB, via, off-chip interconnect, and elastomer mesh probe have been modeled. A complete system-level model, with off-chip interconnects on the WLP device pads, has been developed. The measurement and model demonstrate that the prototype test socket performs at 5 GHz with an insertion loss of about 3 dB. WLP device with Bed-of-Nail interconnects are characterized. Functional test features of the system are also addressed. © 2007 IEEE.
Source Title: IEEE Transactions on Advanced Packaging
URI: http://scholarbank.nus.edu.sg/handle/10635/54653
ISSN: 15213323
DOI: 10.1109/TADVP.2007.898617
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