Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/54531
Title: A new modeling technique for mixed-mode simulation of CMOS circuits
Authors: Samudra, G. 
Lee, T.K.
Keywords: Mixed mode simulation
MOS conductance model
MOS device conductance
Simulation
Issue Date: Aug-1997
Source: Samudra, G.,Lee, T.K. (1997-08). A new modeling technique for mixed-mode simulation of CMOS circuits. Integration, the VLSI Journal 22 (1-2) : 87-99. ScholarBank@NUS Repository.
Abstract: An efficient and accurate simulation of digital circuits is of utmost importance in VLSI design to correctly predict timing performance and to accurately predict electrical waveform at all the nodes which link to analog blocks. To achieve this objective, an improved technique to correctly model the conductance of MOS device for electrical logic simulation (ELogic) of CMOS circuits is proposed [7]. The technique is general and applicable to any integrable analytic device current model. The model is implemented in a well-known mixed-mode simulator iSPLICE3. The examples show that the improved technique is able to correctly predict several complete electrical waveforms with a large voltage step of 1 V with only five logic levels to yield at least an order of magnitude computational time advantage over the circuit simulation with virtually minimal loss in the accuracy.
Source Title: Integration, the VLSI Journal
URI: http://scholarbank.nus.edu.sg/handle/10635/54531
ISSN: 01679260
Appears in Collections:Staff Publications

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