Please use this identifier to cite or link to this item: https://doi.org/10.1142/S0218126603001069
Title: A modified frequency-response masking structure for high-speed FPGA implementation of sharp FIR filters
Authors: Lian, Y. 
Keywords: FIR filter design
High-speed low-power filters
Issue Date: Oct-2003
Source: Lian, Y. (2003-10). A modified frequency-response masking structure for high-speed FPGA implementation of sharp FIR filters. Journal of Circuits, Systems and Computers 12 (5) : 643-654. ScholarBank@NUS Repository. https://doi.org/10.1142/S0218126603001069
Abstract: This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.
Source Title: Journal of Circuits, Systems and Computers
URI: http://scholarbank.nus.edu.sg/handle/10635/54422
ISSN: 02181266
DOI: 10.1142/S0218126603001069
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