Please use this identifier to cite or link to this item:
|Title:||A modified frequency-response masking structure for high-speed FPGA implementation of sharp FIR filters|
|Keywords:||FIR filter design|
High-speed low-power filters
|Source:||Lian, Y. (2003-10). A modified frequency-response masking structure for high-speed FPGA implementation of sharp FIR filters. Journal of Circuits, Systems and Computers 12 (5) : 643-654. ScholarBank@NUS Repository. https://doi.org/10.1142/S0218126603001069|
|Abstract:||This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.|
|Source Title:||Journal of Circuits, Systems and Computers|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Mar 8, 2018
WEB OF SCIENCETM
checked on Feb 7, 2018
checked on Mar 12, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.