Please use this identifier to cite or link to this item: https://doi.org/10.1109/TNANO.2013.2280338
Title: A low-power Low-VDD nonvolatile latch using spin transfer torque MRAM
Authors: Huang, K.
Lian, Y. 
Keywords: Low power
Nonvolatile flip-flop (nvFF)
Nonvolatile latch (nvLatch)
Nonvolatile memory (NVM)
Spin-torque transfer MRAM (STT-MRAM)
Two-phase write approach
Issue Date: 2013
Source: Huang, K., Lian, Y. (2013). A low-power Low-VDD nonvolatile latch using spin transfer torque MRAM. IEEE Transactions on Nanotechnology 12 (6) : 1094-1103. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2013.2280338
Abstract: The high leakage power due to the scaling down of the process nodes has been one of the critical issues in CMOS circuits, especially in the sleep power critical systems. The emerging nonvolatile flip-flops (nvFFs) with fast saving and restoration speed and zero sleep power may be the solution to address the high sleep power issue. However, the "source degeneration" and/or "serial write" issues of the reported works may significantly limit the scalability. We propose a novel nvFF using two-phase write approach and complementary write drivers, which reduces more than 38% power for the saving operation and also scales VDD down to 1 V and below. Our proposed nvFF has the closest flip-flop (FF) performance as the CMOS retention FF. Moreover, it has more than 50% area reduction compared to the smallest nvFF in the prior arts. © 2002-2012 IEEE.
Source Title: IEEE Transactions on Nanotechnology
URI: http://scholarbank.nus.edu.sg/handle/10635/54321
ISSN: 1536125X
DOI: 10.1109/TNANO.2013.2280338
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