Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/51175
Title: FPGA implementation of digital filters synthesized using the frequency-response masking technique
Authors: Lim, Y.C. 
Yu, Y.J.
Zheng, H.Q. 
Foo, S.W. 
Issue Date: 2001
Source: Lim, Y.C.,Yu, Y.J.,Zheng, H.Q.,Foo, S.W. (2001). FPGA implementation of digital filters synthesized using the frequency-response masking technique. Proceedings - IEEE International Symposium on Circuits and Systems 2 : II173-II176. ScholarBank@NUS Repository.
Abstract: The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM.
Source Title: Proceedings - IEEE International Symposium on Circuits and Systems
URI: http://scholarbank.nus.edu.sg/handle/10635/51175
ISSN: 02714310
Appears in Collections:Staff Publications

Show full item record
Files in This Item:
There are no files associated with this item.

Page view(s)

40
checked on Dec 9, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.