Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/49632
Title: Instruction Cache Optimizations in Embedded Real-Time Systems
Authors: DING HUPING
Keywords: Embedded Real-time Systems, Instruction Cache, Partial Cache Locking, Static Analysis, WCET, Worst-case Performance
Issue Date: 16-Aug-2013
Source: DING HUPING (2013-08-16). Instruction Cache Optimizations in Embedded Real-Time Systems. ScholarBank@NUS Repository.
Abstract: Caches are widely employed in modern embedded real-time systems. They bridge the performance gap between the fast CPU and the slow off-chip memory. However, they also introduce timing unpredictability in real-time systems. Existing approaches dealing with timing unpredictability of caches usually employ static cache analysis or full cache locking techniques. However, static cache analysis may produce inaccurate results, while full cache locking may have negative impact on the overall execution time. In this thesis, we propose partial cache locking technique to optimize the worst-case performance of embedded real-time systems. We studies partial instruction cache locking in the context of different architectures and system models in embedded real-time systems. The worst-case performance of the applications is greatly improved, compared to the existing approaches.
URI: http://scholarbank.nus.edu.sg/handle/10635/49632
Appears in Collections:Ph.D Theses (Open)

Show full item record
Files in This Item:
File Description SizeFormatAccess SettingsVersion 
DingHP.pdf2.42 MBAdobe PDF

OPEN

NoneView/Download

Page view(s)

110
checked on Dec 11, 2017

Download(s)

174
checked on Dec 11, 2017

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.