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Title: Tunneling Field-Effect Transistors for Low Power Logic: Design, Simulation and Technology Demonstration
Authors: YANG YUE
Keywords: tunneling transistor, simulation, technology demonstration, gate capacitance, germanium-tin TFET, silicon-carbon source TFET
Issue Date: 6-May-2013
Citation: YANG YUE (2013-05-06). Tunneling Field-Effect Transistors for Low Power Logic: Design, Simulation and Technology Demonstration. ScholarBank@NUS Repository.
Abstract: The tunneling field-effect transistor (TFET) is a promising device candidate to overcome the 60 mV/decade subthreshold swing (S) limitation of the conventional metal-oxide-semiconductor field-effect transistor (MOSFET). TFET exploits gate modulated band-to-band tunneling (BTBT) to achieve a steep S and a high on-state current Ion to off-state current Ioff ratio at a low supply voltage VDD. However, current TFET technology is still under development, and most reported TFETs suffer from low current. This dissertation focuses on development of TFET technology. The gate capacitance of TFET was studied in details. Novel structure, double-gate (DG) TFET with extended source, was designed for drive current enhancement. In addition, Si:C was implemented into Si TFET as the source to ease BTBT and therefore improve the device performance. New substrate material germanium-tin (GeSn), which has small bandgap, was explored for TFET application and GeSn p-channel TFETs is realized for the first time. Descent electrical characteristic was achieved.
Appears in Collections:Ph.D Theses (Open)

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