Please use this identifier to cite or link to this item: https://doi.org/10.1145/1811212.1811220
Title: Modeling shared cache and bus in multi-cores for timing analysis
Authors: Chattopadhyay, S.
Roychoudhury, A. 
Mitra, T. 
Keywords: Multi-core
Shared bus
Shared cache
WCET
Issue Date: 2010
Source: Chattopadhyay, S.,Roychoudhury, A.,Mitra, T. (2010). Modeling shared cache and bus in multi-cores for timing analysis. Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010. ScholarBank@NUS Repository. https://doi.org/10.1145/1811212.1811220
Abstract: Timing analysis of concurrent programs running on multi-core platforms is currently an important problem. The key to solving this problem is to accurately model the timing effects of shared resources in multi-cores, namely shared cache and bus. In this paper, we provide an integrated timing analysis framework that captures timing effects of both shared cache and shared bus. We also develop a cycle-accurate simulation infra-structure to evaluate the precision of our analysis. Experimental results from a large fragment of an in-orbit spacecraft software show that our analysis produces around 20% over-estimation over simulation results. © 2010 ACM.
Source Title: Proceedings of the 13th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2010
URI: http://scholarbank.nus.edu.sg/handle/10635/41932
ISBN: 9781450300841
DOI: 10.1145/1811212.1811220
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