Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/41803
Title: Generating test programs to cover pipeline interactions
Authors: Thanh, N.D.
Roychoudhury, A. 
Mitra, T. 
Mishra, P.
Keywords: Automated test generation
Pipelines
State space exploration
Issue Date: 2009
Source: Thanh, N.D.,Roychoudhury, A.,Mitra, T.,Mishra, P. (2009). Generating test programs to cover pipeline interactions. Proceedings - Design Automation Conference : 142-147. ScholarBank@NUS Repository.
Abstract: Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test-suite generation. Our primary contribution is an automated test-suite generation methodology that covers all possible processor pipeline interactions. To accomplish this automation, we (1) develop a fully formal processor model based on communicating extended finite state machines, and (2) traverse the processor model for on-the-fly generation of short test programs covering all reachable states and transitions. Our test generation method achieves several orders of magnitude reduction in test-suite size compared to the previously proposed formal approaches for test generation, leading to drastic reduction in validation effort. Copyright 2009 ACM.
Source Title: Proceedings - Design Automation Conference
URI: http://scholarbank.nus.edu.sg/handle/10635/41803
ISBN: 9781605584973
ISSN: 0738100X
Appears in Collections:Staff Publications

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