Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/41590
Title: Systematic debugging of real-time systems based on incremental satisfiability counting
Authors: Andrei, Ş.
Chin, W.-N. 
Cheng, A.M.K.
Lupu, M.
Issue Date: 2005
Source: Andrei, Ş.,Chin, W.-N.,Cheng, A.M.K.,Lupu, M. (2005). Systematic debugging of real-time systems based on incremental satisfiability counting. Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS : 519-528. ScholarBank@NUS Repository.
Abstract: Real-time logic (RTL) [1, 2, 3] is useful for the verification of a safety assertion with respect to the specification of a real-time system. Since the satisfiability problem for RTL is undecidable, the systematic debugging of a real-time system appears impossible. This paper provides a first step towards this challenge. With RTL, each propositional formula corresponds to a verification condition. The number of truth assignments of a propositional formula helps to determine the timing constraints which should be added or modified to the system's specification. We have implemented a tool (called SDRTL, [4]) that is able to perform systematic debugging. The confidence of our approach is high as we have evaluated SDRTL on several existing industrial-based applications. © 2005 IEEE.
Source Title: Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
URI: http://scholarbank.nus.edu.sg/handle/10635/41590
ISSN: 15453421
Appears in Collections:Staff Publications

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