Please use this identifier to cite or link to this item:
|Title:||Unified cache modeling for WCET analysis and layout optimizations|
|Source:||Chattopadhyay, S., Roychoudhury, A. (2009). Unified cache modeling for WCET analysis and layout optimizations. Proceedings - Real-Time Systems Symposium : 47-56. ScholarBank@NUS Repository. https://doi.org/10.1109/RTSS.2009.20|
|Abstract:||Presence of instruction and data caches in processors create lack of predictability in execution timings. Hard real-time systems require absolute guarantees about execution time, and hence the timing effects of caches need to be modeled while estimating the Worst-case Execution Time (WCET) of a program. In this work, we consider the modeling of a generic cache architecture which is most common in commercial processors - separate instruction and data caches in the first level and a unified cache in the second level (which houses code as well as data). Our modeling is used to develop a timing analysis method built on top of the Chronos WCET analysis tool. Moreover we use our unified cache modeling to develop WCET-driven code and data layout optimizations - where the code and data layout are optimized simultaneously for reducing WCET. © 2009 IEEE.|
|Source Title:||Proceedings - Real-Time Systems Symposium|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 6, 2017
WEB OF SCIENCETM
checked on Nov 20, 2017
checked on Dec 10, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.