Please use this identifier to cite or link to this item: https://doi.org/10.1145/1878921.1878944
Title: Improved procedure placement for set associative caches
Authors: Liang, Y.
Mitra, T. 
Keywords: Cache miss
Code layout
Instruction cache
Intermediate blocks profile
Memory
Procedure placement
Issue Date: 2010
Source: Liang, Y., Mitra, T. (2010). Improved procedure placement for set associative caches. Embedded Systems Week 2010 - Proceedings of the 2010 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'10 : 147-156. ScholarBank@NUS Repository. https://doi.org/10.1145/1878921.1878944
Abstract: The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boost to an embedded application. Procedure placement is a popular technique that aims to improve instruction cache hit rate by reducing conflicts in the cache through compile/link time reordering of procedures. However, existing procedure placement techniques make reordering decisions based on imprecise conflict information. This imprecision leads to limited and sometimes negative performance gain, specially for set-associative caches. In this paper, we introduce intermediate blocks profile (IBP) to accurately but compactly model cost-benefit of procedure placement for both direct mapped and set associative caches. We propose an efficient algorithm that exploits IBP to place procedures in memory such that cache conflicts are minimized. Experimental results demonstrate that our approach provides substantial improvement in cache performance over existing procedure placement techniques. Furthermore, we observe that the code layout for a specific cache configuration is not portable across different cache configurations. To solve this problem, we propose an algorithm that exploits IBP to place procedures in memory such that the average cache miss rate across a set of cache configurations is minimized.
Source Title: Embedded Systems Week 2010 - Proceedings of the 2010 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'10
URI: http://scholarbank.nus.edu.sg/handle/10635/41243
ISBN: 9781605589039
DOI: 10.1145/1878921.1878944
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