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Title: | Evaluating design trade-offs in customizable processors | Authors: | Bordoloi, U.D. Huynh, P.H. Chakraborty, S. Mitra, T. |
Keywords: | ASIP Multi-objective design space exploration Pareto-optimal curve Processor customization |
Issue Date: | 2009 | Citation: | Bordoloi, U.D., Huynh, P.H., Chakraborty, S., Mitra, T. (2009). Evaluating design trade-offs in customizable processors. Proceedings - Design Automation Conference : 244-249. ScholarBank@NUS Repository. | Abstract: | The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. Unfortunately, identifying the optimal trade-off points turns out to be computationally intractable. In this paper, we present a polynomial-time approximation algorithm to systematically evaluate the design trade-offs. In particular, we explore performance-area trade-offs in the context of multi-tasking real-time embedded applications to be implemented on a customizable processor. Copyright 2009 ACM. | Source Title: | Proceedings - Design Automation Conference | URI: | http://scholarbank.nus.edu.sg/handle/10635/41075 | ISBN: | 9781605584973 | ISSN: | 0738100X |
Appears in Collections: | Staff Publications |
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