Please use this identifier to cite or link to this item: https://doi.org/10.1145/1450135.1450170
Title: Cache-aware optimization of BAN applications
Authors: Liang, Y. 
Ju, L. 
Chakraborty, S. 
Mitra, T. 
Roychoudhury, A. 
Keywords: Body-area networks
Cache
Mobile devices
Sensor networks
Issue Date: 2008
Source: Liang, Y.,Ju, L.,Chakraborty, S.,Mitra, T.,Roychoudhury, A. (2008). Cache-aware optimization of BAN applications. Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 : 149-154. ScholarBank@NUS Repository. https://doi.org/10.1145/1450135.1450170
Abstract: Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring applications need continuous processing of large volumes of data, as a result of which both power consumption and computation bandwidth turn out to be serious constraints for sensor network platforms. This has resulted in a lot of recent interest in design methods, modeling and software analysis techniques specifically targeted towards BANs and applications running on them. In this paper we show that appropriate optimization of the application running on the communication gateway of a wireless BAN and accurate modeling of the microarchitectural details of the gateway processor can lead to significantly better resource usage and power savings. In particular, we propose a method for deriving the optimal order in which the different sensors feeding the gateway processor should be sampled, to maximize cache re-use. Our case study using a faint fall detection application - from the geriatric care domain - which is fed by a number of smart sensors to detect physiological and physical gait signals of a patient show very attractive energy savings in the underlying processor. Alternatively, our method can be used to improve the sampling frequency of the sensors, leading to higher reliability and better response time of the application. Copyright 2008 ACM.
Source Title: Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008
URI: http://scholarbank.nus.edu.sg/handle/10635/40649
ISBN: 9781605584706
DOI: 10.1145/1450135.1450170
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