Please use this identifier to cite or link to this item:
|Title:||DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs|
|Citation:||Maxiaguine, A.,Chakraborty, S.,Thiele, L. (2005). DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs. CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis : 111-116. ScholarBank@NUS Repository.|
|Abstract:||We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our scheme over previously published DVS schemes is its ability to provide hard QoS guarantees while still achieving considerable energy savings. Our scheme can handle workloads characterized by both, the datadependent variability in the execution time of multimedia tasks and the burstiness in the on-chip traffic arising out of multimedia processing. Many previous DVS algorithms capable of handling such workloads rely on control-theoretic feedback mechanisms or prediction schemes based on probabilistic techniques. Usually it is difficult to provide QoS guarantees with such schemes. In contrast, our scheme relies on worst-case interval-based characterization of the workload. The main novelty of our scheme is a combination of offline analysis and runtime monitoring to obtain worst case bounds on the workload and then improving these bounds at runtime. Our scheme is fully scalable and has a bounded application-independent runtime overhead. Copyright 2005 ACM.|
|Source Title:||CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 29, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.