Please use this identifier to cite or link to this item:
|Title:||An inter-core communication enabled multi-core simulator based on simplescalar|
|Source:||Zhong, R.,Zhu, Y.,Chen, W.,Lin, M.,Wong, W.-F. (2007). An inter-core communication enabled multi-core simulator based on simplescalar. Proceedings - 21st International Conference on Advanced Information Networking and Applications Workshops/Symposia, AINAW'07 2 : 758-763. ScholarBank@NUS Repository. https://doi.org/10.1109/AINAW.2007.87|
|Abstract:||In the recent years, multi-core processors prove their extensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among different processing modules. A shared memory scheme is introduced for inter-core communication with a set of shared memory access instructions and communication methods. A synchronization mechanism, which only switches the simulation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms. © 2007 IEEE.|
|Source Title:||Proceedings - 21st International Conference on Advanced Information Networking and Applications Workshops/Symposia, AINAW'07|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 13, 2017
checked on Dec 9, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.