Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICCAD.2004.1382679
Title: Configuration bitstream compression for dynamically reconfigurable FPGAs
Authors: Pan, J.H.
Mitra, T. 
Wong, W.-F. 
Issue Date: 2004
Source: Pan, J.H.,Mitra, T.,Wong, W.-F. (2004). Configuration bitstream compression for dynamically reconfigurable FPGAs. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD : 766-773. ScholarBank@NUS Repository. https://doi.org/10.1109/ICCAD.2004.1382679
Abstract: Field Programmable Gate Arrays (FPGAs) holds the possibility of dynamic reconfiguration. The key advantages of dynamic reconfiguration are the ability to rapidly adapt to dynamic changes and better utilization of the programmable hardware resources for multiple applications. However, with the advent of multi-million gate equivalent FPGAs, configuration time is increasingly becoming a concern. High reconfiguration cost can potentially wipe out any gains from dynamic reconfiguration. One solution to alleviate this problem is to exploit the high levels of redundancy in the configuration bitstream by compression. In this paper, we propose a novel configuration compression technique that exploits redundancies both within a configuration's bitstream as well as between bitstreams of multiple configurations. By maximizing reuse, our results show that the proposed technique performs 26.5-75.8% better than the previously proposed techniques. To the best of our knowledge, ours is the first work that performs inter-configuration compression. ©2004 IEEE.
Source Title: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
URI: http://scholarbank.nus.edu.sg/handle/10635/40559
ISBN: 0780387023
ISSN: 10923152
DOI: 10.1109/ICCAD.2004.1382679
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