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Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASYNC.2006.19
DC FieldValue
dc.titleInterface design for rationally clocked GALS systems
dc.contributor.authorMekie, J.
dc.contributor.authorChakraborty, S.
dc.contributor.authorVenkataramani, G.
dc.contributor.authorThiagarajan, P.S.
dc.contributor.authorSharma, D.K.
dc.date.accessioned2013-07-04T08:02:30Z
dc.date.available2013-07-04T08:02:30Z
dc.date.issued2006
dc.identifier.citationMekie, J., Chakraborty, S., Venkataramani, G., Thiagarajan, P.S., Sharma, D.K. (2006). Interface design for rationally clocked GALS systems. Proceedings - International Symposium on Asynchronous Circuits and Systems 2006 : 160-171. ScholarBank@NUS Repository. https://doi.org/10.1109/ASYNC.2006.19
dc.identifier.isbn0769524982
dc.identifier.issn15228681
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/40358
dc.description.abstractWe investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delayaugmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface, that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique. © 2006 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ASYNC.2006.19
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.doi10.1109/ASYNC.2006.19
dc.description.sourcetitleProceedings - International Symposium on Asynchronous Circuits and Systems
dc.description.volume2006
dc.description.page160-171
dc.identifier.isiut000237342400016
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