Please use this identifier to cite or link to this item:
|Title:||Interface design for rationally clocked GALS systems|
|Citation:||Mekie, J., Chakraborty, S., Venkataramani, G., Thiagarajan, P.S., Sharma, D.K. (2006). Interface design for rationally clocked GALS systems. Proceedings - International Symposium on Asynchronous Circuits and Systems 2006 : 160-171. ScholarBank@NUS Repository. https://doi.org/10.1109/ASYNC.2006.19|
|Abstract:||We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delayaugmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface, that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique. © 2006 IEEE.|
|Source Title:||Proceedings - International Symposium on Asynchronous Circuits and Systems|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Nov 13, 2018
WEB OF SCIENCETM
checked on Oct 30, 2018
checked on Nov 3, 2018
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.