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|Title:||Tolerating process variations in large, set-associative caches: The buddy cache|
|Citation:||Koh, C.-K., Wong, W.-F., Chen, Y., Li, H. (2009). Tolerating process variations in large, set-associative caches: The buddy cache. Transactions on Architecture and Code Optimization 6 (2). ScholarBank@NUS Repository. https://doi.org/10.1145/1543753.1543757|
|Abstract:||One important trend in today's microprocessor architectures is the increase in size of the processor caches. These caches also tend to be set associative. As technology scales, process variations are expected to increase the fault rates of the SRAM cells that compose such caches. As an important component of the processor, the parametric yield of SRAM cells is crucial to the overall performance and yield of the microchip. In this article, we propose a microarchitectural solution, called the buddy cache that permits large, set-associative caches to tolerate faults in SRAM cells due to process variations. In essence, instead of disabling a faulty cache block in a set (as is the current practice), it is paired with another faulty cache block in the same setthe buddy. Although both cache blocks are faulty, if the faults of the two blocks do not overlap, then instead of losing two blocks, buddying will yield a functional block from the nonfaulty portions of the two blocks. We found that with buddying, caches can better mitigate the negative impacts of process variations on performance and yield, gracefully downgrading performance as opposed to catastrophic failure. We will describe the details of the buddy cache and give insights as to why it is both more performance and yield resilient to faults. © 2009 ACM.|
|Source Title:||Transactions on Architecture and Code Optimization|
|Appears in Collections:||Staff Publications|
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