Please use this identifier to cite or link to this item: https://doi.org/10.1109/MDT.2004.60
Title: Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms
Authors: Maxiaguine, A.
Chakraborty, S. 
Künzli, S.
Thiele, L.
Issue Date: 2004
Source: Maxiaguine, A.,Chakraborty, S.,Künzli, S.,Thiele, L. (2004). Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms. IEEE Design and Test of Computers 21 (5) : 368-377. ScholarBank@NUS Repository. https://doi.org/10.1109/MDT.2004.60
Abstract: Scheduling on-chip resources using analytical technques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standards event models used in real-time scheduling and accurately captures the variability in task execution requirements.
Source Title: IEEE Design and Test of Computers
URI: http://scholarbank.nus.edu.sg/handle/10635/39776
ISSN: 07407475
DOI: 10.1109/MDT.2004.60
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