Please use this identifier to cite or link to this item: https://doi.org/10.1145/2086696.2086701
Title: Bahurupi: A polymorphic heterogeneous multi-core architecture
Authors: Pricopi, M.
Mitra, T. 
Keywords: Instruction-level parallelism
Multi-core
Thread-level parallelism
Issue Date: 2012
Source: Pricopi, M., Mitra, T. (2012). Bahurupi: A polymorphic heterogeneous multi-core architecture. Transactions on Architecture and Code Optimization 8 (4). ScholarBank@NUS Repository. https://doi.org/10.1145/2086696.2086701
Abstract: Computing systems have made an irreversible transition towards parallel architectures with the emergence of multi-cores. Moreover, power and thermal limits in embedded systems mandate the deployment of many simpler cores rather than a few complex cores on chip. Consumer electronic devices, on the other hand, need to support an ever-changing set of diverse applications with varying performance demands. While some applications can benefit from thread-level parallelism offered by multi-core solutions, there still exist a large number of applications with substantial amount of sequential code. The sequential programs suffer from limited exploitation of instruction-level parallelism in simple cores. We propose a reconfigurable multicore architecture, called Bahurupi, that can successfully reconcile the conflicting demands of instruction-level and thread-level parallelism. Bahurupi can accelerate the performance of serial code by dynamically forming coalition of two or more simple cores to offer increased instruction-level parallelism. In particular, Bahurupi can efficiently merge 2-4 simple 2-way out-of-order cores to reach or even surpass the performance of more complex and power-hungry 4-way or 8-way out-of-order core. Compared to baseline 2-way core, quad-core Bahurupi achieves up to 5.61 speedup (average 4.08 speedup) for embedded workloads. On an average, quad-core Bahurupi achieves 17% performance improvement and 43% improvement in energy consumption compared to 8-way out-of-order baseline core on a diverse set of embedded benchmark applications. © 2012 ACM.
Source Title: Transactions on Architecture and Code Optimization
URI: http://scholarbank.nus.edu.sg/handle/10635/39768
ISSN: 15443566
DOI: 10.1145/2086696.2086701
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