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Title: Dynamic cache contention detection in multi-threaded applications
Authors: Zhao, Q.
Koh, D.
Raza, S.
Amarasinghe, S.
Bruening, D.
Wong, W.-F. 
Keywords: Cache Contention
Dynamic Instrumentation
False Sharing
Shadow Memory
Issue Date: 2011
Citation: Zhao, Q., Koh, D., Raza, S., Amarasinghe, S., Bruening, D., Wong, W.-F. (2011). Dynamic cache contention detection in multi-threaded applications. ACM SIGPLAN Notices 46 (7) : 27-37. ScholarBank@NUS Repository.
Abstract: In today's multi-core systems, cache contention due to true and false sharing can cause unexpected and significant performance degradation. A detailed understanding of a given multi-threaded application's behavior is required to precisely identify such performance bottlenecks. Traditionally, however, such diagnostic information can only be obtained after lengthy simulation of the memory hierarchy. In this paper, we present a novel approach that efficiently analyzes interactions between threads to determine thread correlation and detect true and false sharing. It is based on the following key insight: although the slowdown caused by cache contention depends on factors including the thread-to-core binding and parameters of the memory hierarchy, the amount of data sharing is primarily a function of the cache line size and application behavior. Using memory shadowing and dynamic instrumentation, we implemented a tool that obtains detailed sharing information between threads without simulating the full complexity of the memory hierarchy. The runtime overhead of our approach - a 5× slowdown on average relative to native execution - is significantly less than that of detailed cache simulation. The information collected allows programmers to identify the degree of cache contention in an application, the correlation among its threads, and the sources of significant false sharing. Using our approach, we were able to improve the performance of some applications by up to a factor of 12. For other contention-intensive applications, we were able to shed light on the obstacles that prevent their performance from scaling to many cores. Copyright © 2011 ACM.
Source Title: ACM SIGPLAN Notices
ISSN: 15232867
DOI: 10.1145/2007477.1952688
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