Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/33336
Title: Low-voltage Low-power Switched-Capacitor ?S Modulator Design
Authors: YANG ZHENGLIN
Keywords: delta-sigma modulator, switched-capacitor circuits, low voltage, low power, CMOS, input-feedforward topology
Issue Date: 7-Jan-2012
Source: YANG ZHENGLIN (2012-01-07). Low-voltage Low-power Switched-Capacitor ?S Modulator Design. ScholarBank@NUS Repository.
Abstract: This thesis studies a topic of low-voltage low-power ?S modulator for audio-band applications. First of all, state-of-the-art analog-to-digital converters (ADCs) are briefly reviewed and thus ?S converters are motivated for the circuit non-idealities of modern CMOS technologies. Then basic theory of ?S modulator is briefly introduced and followed by the review of various frequently used topologies and circuit implementations. After that, we briefly review low-voltage low-power design issues and techniques. Finally, two design examples are presented with their measured results. The first prototype chip which employs a 2-tap FIR filter to reduce the power consumption consumes 99.7 ?W from a 0.7-V supply voltage. When clocked at 4 MHz, the modulator achieves a peak SNDR of 87.0 dB over a 20-kHz signal bandwidth. The second prototype chip combining double sampling technique with input-feedforward topology achieves 81.7 dB of SNDR while consuming 35.2 ?W from a 0.5-V supply voltage.
URI: http://scholarbank.nus.edu.sg/handle/10635/33336
Appears in Collections:Ph.D Theses (Open)

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