Please use this identifier to cite or link to this item: http://scholarbank.nus.edu.sg/handle/10635/32590
Title: Method to form shallow trench isolation structures for borderless contacts in an integrated circuit
Authors: GOH, KENNY HUA KOOI
CHAN, LAP
YAP, KOK SIONG 
Issue Date: 1-May-2001
Source: GOH, KENNY HUA KOOI,CHAN, LAP,YAP, KOK SIONG (2001-05-01). Method to form shallow trench isolation structures for borderless contacts in an integrated circuit. ScholarBank@NUS Repository.
Abstract: A method of forming shallow trench isolation trenches for use with borderless contacts is achieved. A silicon nitride layer protects the shallow trench oxide layer from overetch damage. A silicon substrate is provided. A pad oxide layer is grown. A polishing stop layer, of polysilicon or silicon nitride, is deposited. The polishing stop layer, pad oxide layer, and silicon substrate are patterned to form the shallow trenches. A trench oxide layer is deposited to fill the shallow trenches. The trench oxide layer is polished down with the polishing stop layer as a polishing stop. The trench oxide layer is etched down to a level below that of the pad oxide layer. A silicon nitride layer is deposited. A polishing layer of oxide is deposited. The polishing layer and the silicon nitride layer are polished down with the polishing stop layer as a polishing stop. The polishing stop layer is etched away. The silicon nitride layer is etched to remove vertical sidewalls. The polishing layer and the pad oxide layer are etched away with the silicon nitride layer as etching stop to complete the shallow trench isolations.
URI: http://scholarbank.nus.edu.sg/handle/10635/32590
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